The present invention relates to a semiconductor device and method for manufacturing same. More particularly, it relates to a semiconductor memory device and a method for fabrication with improved resolution and multilevel interconnections using a damascene technique.
As the integration density of integrated circuit devices increases, efforts are being concentrated on improving exposure techniques so as to obtain a fine pattern that keeps pace with high integration density. As a recent trend, the wavelength of exposing light for photolithography is getting shorter and shorter, for example, from g-line (wavelength:436 nm), i-line (wavelength:365 nm) to KrF excimer laser (wavelength:248 nm). More recently, one promising candidate is ArF excimer laser (wavelength:193 nm). Formation of a fine pattern device can allow improved integrated circuit performance and reduced fabrication cost through improved production performance.
Photolithographic resolution for fine pattern formation is proportional to the wavelength of the exposing light and a constant (K1), and inversely proportional to the numerical aperture (NA). The constant K1 is related to the resist quality and the resolution technique used. Based on recently used NA, resist quality and resolution techniques, it is believed that resolution limit is 0.3 microns with i-line and 0.15 microns with KrF. In the case of ArF, it is generally expected that the resolution limit will be 0.10 microns.
The above calculated resolution limits assume optimal conditions. It is difficult, however, to maintain such optimal conditions in practice. Rather, the resolution limit is greatly affected by the process conditions, for example, variable topology of the substrate, in the photoresist layer due to topology and the reflection rate of the patterning material. Furthermore, in practice, other factors affect the resolution limit, for example, alignment margin and the process window (based on such factors as the level of planarization and the aspect ratio).
To overcome the above mentioned factors which affect the resolution limit in practice, the damascene technique has been widely used for metal interconnection. This technique is preferable due to the high reflection rate of metal. Further damascene avoids difficulty in etching a thick metal layer as in the conventional metal interconnection process, which comprises: depositing metal on an insulating layer; forming a photoresist layer; patterning the photoresist layer; and etching the metal layer using the patterned photoresist layer.
A conventional damascene process may comprise the following steps. First, a groove for interconnection is formed in the insulating layer. Copper is buried in the groove by a CVD (chemical vapor deposition) technique or a sputter/reflow technique. Planarization is then carried out to remove copper outside of the groove and thereby to form damascene interconnection.
However, there are some problems with the conventional damascene technique in application to a metal pattern or a contact hole of 0.5 microns or less. Particularly, an already formed contact hole can be enlarged during the formation of groove by the damascene technique. One possible approach to overcome this problem is to form a small size contact hole. However, as the degree of integration density increases, formation of small size contact holes is getting more and more difficult. Another possibility is to form a groove before the formation of the contact hole. This approach requires that the photoresist pattern for the contact hole be formed in the already formed groove. However, it is difficult to form a photoresist pattern in deep and small size grooves.
The present invention is directed to overcoming or at least reducing the effects of one or more of the problems set forth above.
In accordance with one aspect of the invention there is provided a method in which a dual damascene metal interconnection is formed in the peripheral region using a material layer pattern. Preferably, the material layer pattern has a low reflection rate. In accordance with this method, also formed is a capacitor in the cell array region using the same material layer pattern.
More specifically, a first insulating layer is formed on a semiconductor substrate having the cell array region and the peripheral region. The material layer pattern is then formed on the first insulating layer. The material layer pattern has opening portions which define a contact hole for storage node in the cell array region and define a contact hole for metal interconnection in the peripheral region. The material layer pattern is made of a material that has an etching selectivity with respect to the first insulating layer and later-formed second insulating layer. For example, it may be made of a material selected from the group consisting of an undoped polysilicon, a nitride material, SiON and Al2O3.
A second insulating layer is formed on the material layer pattern. Groove photoresist pattern is Men formed on the second insulating layer and it has opening portions aligned over the opening portions defined by the material layer pattern. Using the photoresist pattern, the second is etched down to the material layer pattern to form a first opening. In success, exposed portion of the first insulating layer by the opening portions of material layer pattern is selectively etched to form a second opening self aligned to the first opening and thereby to form dual damascene opening in the peripheral region.
The dual damascene opening is then filled with a metal and planarized to form damascene metal interconnection to the semiconductor substrate.
The material layer pattern also is used for formation of storage node in the cell array region. After forming the damascene metal line in the peripheral region, a third insulating layer is formed on the entire surface of the semiconductor substrate. Another photoresist pattern is formed on the third insulating layer aligned over the opening portions of the material layer pattern and has opening portions which defines storage node. Using another photoresist pattern, third and second insulating layers are etched down to the material layer pattern to form a third opening. The exposed first insulating layer by the material layer pattern is then etched to form a fourth opening exposing desired portion of the semiconductor substrate. Conductive material is deposited in the third and fourth openings to form the storage node in the cell array region that is electrically connected to the desired portion of the semiconductor substrate.
Alternatively, process sequence can be reversed. Namely, after the storage node is formed in the cell array region, the dual damascene metal line can be formed in the peripheral region.
In accordance with another aspect of the invention, a semiconductor device is provided. The semiconductor device comprises a first insulating layer formed on a semiconductor substrate having a cell array region and a peripheral region. A material layer pattern formed on the first insulating layer, the material layer pattern having first opening portions at the cell array region and second opening portions at the peripheral region. a second insulating layer formed on the material layer pattern. A capacitor is formed in the second insulating layer and electrically connected to the semiconductor substrate through an opening in the first insulating layer that is self aligned with the first opening portions of the material layer pattern at the cell array region. Metal interconnections are formed in the second insulating layer and electrically connected to the semiconductor substrate through openings in the first insulating layer. The metal interconnections are self aligned with the second opening portions of the material layer pattern at the peripheral region.